SOURCE=0, ENBL=0, TRIG=0
Channel Configuration register
| SOURCE | DMA Channel Source (Slot) 0 (0): Disable_Signal 2 (2): UART0_Rx_Signal 3 (3): UART0_Tx_Signal 4 (4): UART1_Rx_Signal 5 (5): UART1_Tx_Signal 6 (6): UART2_Rx_Signal 7 (7): UART2_Tx_Signal 8 (8): UART3_Rx_Signal 9 (9): UART3_Tx_Signal 14 (14): I2S0_Rx_Signal 15 (15): I2S0_Tx_Signal 16 (16): SPI0_Rx_Signal 17 (17): SPI0_Tx_Signal 18 (18): SPI1_Rx_Signal 19 (19): SPI1_Tx_Signal 22 (22): I2C0_Signal 23 (23): I2C1_Signal 24 (24): FTM0_Channel0_Signal 25 (25): FTM0_Channel1_Signal 26 (26): FTM0_Channel2_Signal 27 (27): FTM0_Channel3_Signal 28 (28): FTM0_Channel4_Signal 29 (29): FTM0_Channel5_Signal 30 (30): FTM0_Channel6_Signal 31 (31): FTM0_Channel7_Signal 32 (32): FTM1_Channel0_Signal 33 (33): FTM1_Channel1_Signal 34 (34): FTM2_Channel0_Signal 35 (35): FTM2_Channel1_Signal 40 (40): ADC0_Signal 42 (42): CMP0_Signal 43 (43): CMP1_Signal 45 (45): DAC0_Signal 47 (47): CMT_Signal 48 (48): PDB0_Signal 49 (49): PortA_Signal 50 (50): PortB_Signal 51 (51): PortC_Signal 52 (52): PortD_Signal 53 (53): PortE_Signal 54 (54): AlwaysOn54_Signal 55 (55): AlwaysOn55_Signal 56 (56): AlwaysOn56_Signal 57 (57): AlwaysOn57_Signal 58 (58): AlwaysOn58_Signal 59 (59): AlwaysOn59_Signal 60 (60): AlwaysOn60_Signal 61 (61): AlwaysOn61_Signal 62 (62): AlwaysOn62_Signal 63 (63): AlwaysOn63_Signal |
| TRIG | DMA Channel Trigger Enable 0 (0): Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 1 (1): Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in Periodic Trigger mode. |
| ENBL | DMA Channel Enable 0 (0): DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. 1 (1): DMA channel is enabled |